The present invention relates in general to voltage level converter circuits, and in particular to a fast TTL to CMOS level converter circuit with low standby current.
The voltage levels for a logic high and a logic low are different in TTL circuits as compared to CMOS circuits. Therefore, CMOS logic circuits require voltage converting buffers at their inputs to be able to accept TTL signals. In most CMOS designs the input buffer is a CMOS inverter with an otherwise unusual PMOS to NMOS channel width ratio of from 1:3 to as much as 1:8. This ratio skews the inverter trip point to around 1.4 volts such that when the input voltage is 2.0 volts (TTL logic high) the output is near ground (CMOS logic low), and when the input voltage is 0.8 volts (TTL logic low) the output is near the power supply V.sub.cc (CMOS logic high).
Because the PMOS transistor is inherently weaker than the NMOS transistor, to obtain optimal speed, typical CMOS inverters use a PMOS to NMOS transistor size ratio of approximately 2:1. Therefore, when the ratio of the transistor sizes in a CMOS inverter is skewed such that the PMOS transistor is further weakened, the inverter slows down significantly when it is used to drive a large capacitive load. One way to speed up the inverter is to scale up the widths of both the N and PMOS transistors. However, this results in large amounts of current through the inverter when the input is at 2 volts (the TTL input high voltage termed V.sub.ih) and both transistors are on. Therefore, power dissipation requirements place a limit on the size of the transistors.
A second technique to speed up the buffer inverter is to limit its capacitive loading. This is accomplished by adding a chain of inverters, each with increasing size to build up to an adequate power level to drive the internal fanouts of the input signal. This way the first inverter with skewed transistor size ratio drives the gate of the succeeding inverter only. This solution is typical of current design practices. However, since each inverter in the chain has a finite delay to pass the input signal, the inverter chain results in additional delays.
During the early development of the MOS technology, depletion mode NMOS transistors where used as load devices in MOS circuit designs. By implanting n-type impurities in the channel region of an enhancement mode NMOS device, a strongly conducting channel can be obtained even with a gate to source voltage (V.sub.gs) of zero. The resulting NMOS transistor is called a depletion device, and typically has threshold voltage V.sub.td in the range of -1 to -4 volts.
Using depletion devices as load transistors, a popular buffering technique known as the "depletion-depletion super buffer" was frequently used to drive large fanout capacitances. FIG. 1 shows a typical depletion-depletion super buffer circuit. This circuit has the advantage of being twice as fast as a conventional one stage depletion NMOS inverter when the output is rising, and about 10% faster when the output is falling. This is due to the fact that for a single stage depletion load inverter, the gate of the diodeconnected depletion device is connected to the output of the inverter (also the source of the depletion device) which could be slow when driving a large capacitive load. In the case of the two stage supper buffer of FIG. 1, the gate of sourcefollower depletion load 110 of the second stage is driven by the output of the first stage, node 100, which rises to V.sub.cc at a much faster rate due to the limited capacitance on node 100. This allows the output at the source terminal of depletion device 110 to rise to V.sub.cc at a faster rate.
The major drawback of the super buffer is large power dissipation. When the input is high and the output is low, the super buffer circuit dissipates large amounts of current. For this reason, super buffers were only used when they were truly required.
Taken individually, each of the above circuit techniques pays too high a power dissipation price for the respective speed improvement gained.
From the above it can be seen that there is a need for a high speed voltage level converting circuit capable of driving large capacitive loads while dissipating small standby current.